• Minimum experience: 3 years+
• Job location: Bangalore
• Job code: Category Title – Graphene (e.g.: Automation Test Engineer – Graphene)
• Steps to apply is mentioned at end.

Automation Test Engineer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Location: Bangalore

Job Requirements:

• 4-8 years’ experience in C / TCL programming on Windows or Linux
• Knowledge of Java or scripting languages like Python/Perl is a plus
• Experience on L2, L3, L7, DSL, WLAN, 802.1X, QoS and IPv6
• Strong analytical skills for problem abstraction
• Strong knowledge of IP-based networking protocols
• Familiarity with standard software engineering practices for version control, configuration management, testing, root cause analysis, and quality assurance.

NP Fast Path Engineer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 4 to 7 years

Location: Bangalore

Job Requirements:

• Must have good experience in developing data plane / control plane solutions using Network Processors (Cavium / Intel / FreeScale)
• Should have hands-on experience in developing data-plane features like IP Forwarding (L3 lookup), ACL, Link Aggregation, NAT, VLAN, Qos, IPSec, DPI etc
• Experience in developing data plane modules like GTP, PDCP, RoHC etc. for LTE products will be an added advantage (like MME, SAE-GW, eNB)
• Must be very familiar with Cavium Simple Executive SDK
• Must have very good understanding of the TCP/IP networking

NP Fast Path Engineer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 4 to 7 years

Location: Bangalore

Job Requirements:

• Knowledge of 3GPP specifications related to MME, GTP, Gx, Gy, Diameter, Radius, PCEF
• Analysis & Maintenance, Design & Dev of S/W modules for MME, PGW/SGW CallP.
• Field issues analysis and support for released PKGs on CallP modules at MME, PGW/SGW
• Designing and developing of additional features/enhancements of EPC Call Processing modules
• Analyze the new requirements from operators, make impact analysis and prepare document
• Experience in NETCONF/YANG modeling

Senior IMS/VoLTE Developer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Location: Bangalore

Job Requirements:

• 8 to 10 years with development expertise
• Development experience in IMS, VoIP, VoLTE and RCS
• Must have worked on at least one or more 3GPP Rx, GX, Gy, S9, S6a interfaces from Core network towards IMS
• Expertise on end-to-end VoLTE network architecture, call flow and verification with commercial UEs
• Prior experience in leading LTE feature design and development required, strong in C programming language
• Development and testing in Unix/Linux environment and debugging tools (wireshark, gdb, gcc, other static/dynamic code analysis tools)
• Knowledge of multi-thread programming required, exposure to Agile methodologies and exposure to configuration management tools such as Clearcase/ Git.
• Preferred to have TTCN expertise

DevOps Engineer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 3-6 years

Location: Bangalore

Job Requirements:

• Programming experience C or C++ or C/Java on Unix/Linux OS
• Hands on Scripting experience Python [for development] is mandatory
• Hands on experience in using DevOps tools is mandatory.

DSP Engineer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 4-8 years

Location: Bangalore

Job Requirements:

• Strong experience in Speech/video codec development/integration on Intel/TI platform.
• Strong C++ Coding, Object Oriented design.
• Working & Debugging on Linux platform, Linux IPC, multithreaded and multicore environment, exposure to tools like (GDB, DDD, Val grind, Gtest).
• Preferred: AVCodecs/ FFmpeg, VOIP domain.

MRF Platform Engineer (Cloud)

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 4-8 years

Location: Bangalore

Job Requirements:

• Strong C and System programming with multi-threading, Socket Programming and
• debugging skills, experience in architecture/design/coding activities for complex features/subsystems
• Strong knowledge of networking TCP/IP stacks, Firewall, VLAN and Bridging.
• Hands-on experience and proficient in Python, Perl and shell script.
• Preferred: Hands-on experience in setting up Hypervisors (KVM, Xen) and Cloud Infrastructure management software (Open stack, OpenStack Networking, OVS, vCloud).

MRF OAMP Engineer (Java/C++)

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 4-8 years

Location: Bangalore

Job Requirements:

• Strong knowledge on Core Java and J2EE/C++.
• Strong knowledge on Swings, Struts, Hibernate and EJB’s.
• Working experience on HTML, CSS, JSP, JavaScript, JASPER, JMX and Web Services.
• Preferred: EMS/NMS domain.

Embedded developer – COM & Flexray

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 3-5 years

Location: Bangalore

Job Requirements:

• Good overview on Microcontroller and Embedded Systems
• Very good in C programming skills
• Hands on experience with CAN, Flexray & AUTOSAR architecture
• Automotive domain (embedded C) experience
• Interfacing with clients for business requirement gathering, conducting system analysis and finalizing technical / functional specifications.
• Hands on experience of using tools like Canalyzer etc.
• Knowledge of software configuration management tools like Clearcase etc.

CORD Developer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 4-8 years

Location: Bangalore

Job Requirements:

• Strong knowledge in Networking (DHCP), Linux
• Domain: SDN OR Virtualization & Orchestration
• Programming: Hands on experience in Python, Java, Ansible

Storage Platform Firmware Development Engineer

Qualification: Bachelor’s or Master’s Degree in Computer Science / Engineering or Electrical Engineering.

Experience: 3-10 years

Location: Bangalore

Job Requirements:

• Strong C/C++/Python Programming skills on System On Chip (SoC)/FPGA/Embedded
• platforms – Bitwise, logical and algorithmic skills
• Knowledge of Firmware Architecture
• Good Problem Solving, Logical reasoning and Communication skills
• Development Platform skills – Windows/Linux/RTOS
• Code Debugging skills using JTAG
• In depth knowledge of any one of the Storage Protocols –
• SATA/SCSI/SAS/NVMe/PCIe/RAID/USB/UFS/iSCSI/FC/InfiniBand
• In depth knowledge of NAND Flash Architecture

How to apply for this Job Opening?

For more information upload your resume here with proper job code, subject and details.Other openings can be checked in Job Vacancies

Note: Only shortlisted candidates will get a call for interview.

The post ESW experts hiring – Graphene Semiconductor Services appeared first on JumpWhere.

• Minimum experience: 3 years+
• Job location: Bangalore
• Job code: Category Title – Graphene (e.g.: Memory compiler & Layout – Graphene)
• Steps to apply is mentioned at end.

Memory compiler & Layout

Experience: 3-8 years
Bachelor’s Degree Electrical Engineering
Job Description:

• Mask design work on various building blocks of memory or Register file design eg. Drawing mux cells, decoders, memory control, sense amplifiers etc.
  • Drawing memory core arrays with proper termination at edges, corners and straps.
  • The top level integration of memory instances in memory compiler environment.
  • Regression DRC, LVS, density clean-up of memory instances across memory compiler space.
  • The IR/EM testing and fixes of memory instances.

Skills required:

• Experience in memory mask design.
• Should have experience working in technologies 45nm and below.
• Should have experience in drawing memory core arrays, write drivers and control circuits.
• Should have sound knowledge of DFM concepts; knowledge of double patterning and coloring concepts are a plus.
• Knowledge of SKILL scripting language is preferred

Analog Layout Engineer

Experience: 4 – 8 yrs
Bachelor’s Degree Electrical Engineering/ Master’s Degree
Job Description:

• 4 years of industry experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration
• Must have experience in handling full chip layout and integration using state of the art I.C layout tools
• Experience with Cadence Virtuoso-XL and Mentor Graphics Caliber physical verification tools is a must.
• Experience in DRC, LVS, ERC, Antenna, and post layout extraction.
• Key skills: DRC,LVS,Mixed Signal Layout Design, Analog Layout

Analog Design Engineer

Experience: 2 – 8 yrs
Bachelor’s Degree Electrical Engineering/ Master’s Degree
Job Description:

• You will be a member of the Analog Design team. Your responsibilities will include (but are not limited to):
• Custom circuit design and simulation.
• Custom physical design, extraction, and co-optimization.
• Process, device, template evaluation, and characterization.
• Understand and contribute to methodology development.
• High speed serial/parallel data links (multi Gb/s), PHY circuits, Transceivers, Serializer-Deserializer, PLLs, Clock, and Data Recovery circuits familiarity.
• High speed circuit design in Tx / Rx / Clocking / Reference circuits and low power techniques, silicon reliability, mixed signal design methodology and tools.
• Analog simulators like Cadence, Spice, and System tools like Matlab.

Standard Cell Layout

Experience: 2 – 8 yrs
Bachelor’s Degree Electrical Engineering/ Master’s Degree
Job Description:

• At least 3 years of experience in VLSI layout design or ASIC design automation, CAD tool development and tool integration
• The Candidate will be responsible for Automation of standard cell and custom cell design flow. Automation of standard cell and custom cell library release procedures, customizing tool flows for characterization of standard cells and automation of LPE extraction flow.
• Follow design guidelines set forth by the Engineering and Layout design leads in delivering high quality standard/custom cell layouts in a timely manner.
• In-depth proficiency in sub-micron technologies 28nm, 20soc, 16nm, 14nm, 10nm.
• Good understanding of the standard cell library architecture, ASIC design flow and semi-custom design flows.
• Hands-on layout experience of digital ASICs in leading edge CMOS processes 28nm, 20nm, 16nm, 14nm, 10nm.
• Tools: Cadence (preferably 6.1* Open Access version), Cadence VXL, Mentor Graphics Calibre verification suite, Calibre RVE.

RF Layout Engineers

Experience: 3-6 Years
Bachelor’s Degree Electrical Engineering/ Master’s Degree
Job Description:

• Candidate should work independently on block level and chip level analog layout design, coordinating with the circuit designer & the layout lead .
• Candidate should have 3+ years of hands-on experience in Analog or RF layout.
• Custom layout experience in high frequency circuits such as LNAs, Mixers, VCOs, DAC, ADC, PLL, LDO etc.
• Work closely with the design engineers and layout engineers in designing and successfully delivering analog layouts.
• Full Understanding of IC fabrication and reliability issues.
• Full familiarity with Cadence-Virtuoso, PVS, ASSURA and Calibre tools .
• Knowledge of various analog layout techniques, understanding of various circuit principles as affected by layout such as speed, capacitance, power, noise and area.
• Should have worked on Analog IC Layout, DRC/LVS/Antenna/LPE Checks, CMOS/BiCMOS Device Physics, CMOS/BiCMOS Fabrication Knowledge.
• Outstanding written and verbal communication skills.

Physical Design

Experience : 3 to 12 yrs
Qualification : BE/BTech, ME/MTech ( VLSI Domain )
Location : Bangalore
Role and responsibility:

• Ability to execute block level and SOC level P&R and Timing closure activities.
• Will be responsible for owning up IR/EM/ESD simulations for the various CPU .
• Perform RTL2GDS or Netlist2GDS on blocks and/or fullchip for SoC designs executed by Foundry.
• This design group is designing some of the critical SoCs using Intel foundry design kits.
• The key responsibility is to independently own and converge partitions and sections on 14nm and below processes and execution in converging their blocks for implementation and timing

Job requirements:

• Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm,16nm,14nm & below ).
• Strong Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
• Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required. Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus.
• Expertise in Synopsys IC compiler, Magma or Cadence SOC encounter physical design tools.
• Skill and experience in scripting using Tcl or Perl is highly desirable.

SOC Verification

Experience : 3 to 10 yrs
Qualification : BE/BTech, ME/MTech ( VLSI Domain )

Job Description:

• Development of verification plans
• Verification environments
• Test cases and ensuring coverage and performance goals are achieved for IP and SOC level.
• Working Knowledge of ARM processors.
• HVLs/Tools: SV, UVM, C
• Domain: Networking, DDR2/3/4, Ethernet PCIe

IP Verification

Experience: 3 to 10 yrs
Qualification : BE/BTech, ME/MTech ( VLSI Domain )

Job Description:

• 4 – 10 years experience in Design Verification
• Strong System Verilog or Specman expertise OVM/UVM/eRM expertise highly desired
•  Good knowledge of protocols
• Ability and desire to learn new methodologies, languages, protocols etc

DFT

Experience : 3 to 10 yrs
Qualification : BE/BTech, ME/MTech ( VLSI Domain )
Job Description:

• Strong knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC –level for mixed signal designs.
• Experience in using Mentor DfT tools, Cadence RC and simulator tools
• Define DfT Strategy and Requirement Specification for the design
• DfT verification for gate-level and timing simulations
• Work cross sites with design team to define and implement DfT.
• Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.
• Work with STA engineer to define timing constraints for DfT modes
• Support Test engineer in silicon debug and pattern delivery for ATE
• Experience in RTL coding, shell scripting
• Experienced in handling analog DfT simulations
• Be fluent with all common concepts of DfT and DfT tools

Synthesis/STA

Experience: 3 to 10 yrs
Qualification: BE/BTech, ME/MTech ( VLSI Domain )
Job Description:

• Expertise in Synthesis using Synopsys DC/ Cadence RTL Compiler based tool set
• Expertise in Synthesis for High Performance , Low Power, Low Area based Flows
• Expertise in SDC Constraints Creation and constraints cleanup based on the timing issues
• Expertise in Formal & Low Power Verification using Synopsys/Cadence based tools
• Expertise in Running PTSI/ETS tools for Timing Sign-off and generating timing ECO based on the timing issues
• Expertise in Multi-mode multi-corner STA analysis on SoC
• Skill and experience in scripting using Tcl or Perl is highly desirable.

RTL Design

Experience : 3 to 10 yrs
Qualification : BE/BTech, ME/MTech ( VLSI Domain )
Job Description:

• Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL
• Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols
• Has good knowledge on various tools viz Spyglass, 0-in, DC-Compiler, Prime time, PTPX, Power-Artist,LEC etc
• Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus.

How to apply for this Job Opening?

For more information upload your resume here with proper job code, subject and details.Other openings can be checked in Job Vacancies

Note: Only shortlisted candidates will get a call for interview.

The post VLSI experts hiring – Graphene Semiconductor Services appeared first on JumpWhere.