Eligibility Criteria for Test Engineer Intern Job Openings at Xiaomi:

• Education: BE/B.Tech / MCA / Msc

• Skills: Understanding of Software Testing and Bug Life cycle.

• Last date: ASAP

• Job Location: Bengaluru

• Batch: Any

Key Roles and Responsibilities of the Intern Job Openings at Xiaomi:

• Understanding of Software Testing and Bug Life cycle.
• Be able to work independently on a project-by project basis and also work in a collaborative and fast-paced team environment
• Be able to analyze and provide solutions to any challenges during testing.
• Basic understanding of Power, Voltage, current, and watts relation.
• Good communication skills.
• Any Automation language knowledge is preferable.

About the Company:

https://careers.xiaomi.com/

To Apply for Xiaomi Interview Process Click Below, Link:

Test Engineer Intern Job Openings at Xiaomi

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The post Freshers Jobs – Test Engineer Intern Job Openings at Xiaomi, Bangalore appeared first on JumpWhere.

• ATE Test Engineers
• Physical Design
• IP/SOC Verification
• RTL Design
• DFT
• Synthesis/STA
• AMS Verification

Note: Below is the description of each of the job role mentioned above for VLSI division. Please read till end of the details mention to APPLY for the job.

Job Role: ATE Test Engineers (Bangalore/Singapore)

Job Description:

• To convert an existing micro-controller test program from Teradyne J750 to Verigy 93K
• Field of Knowledge: Test and Verification Engineering
• Scope of work: Responsible to test program conversion from J750 to v93K Responsible for v93K tester design
• Knowledge: Teradyne J750 programmin
• Knowledge: v93K, VLSI

Qualification: B.E or M.Tech in Electronics, Electrical, VLSI

Year of experience: 3-8 years

Job Role: Physical Design

Year of experience: 4 to 12 yrs

Qualification: BTech/ MTech in ECE/ EEE from IITs/ RECs/ BITS

Job Description:

• Implementation of multi million gate SoC designs in cutting edge process technologies (65nm, 40nm, 28nm& below ).
• Strong Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
• Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required. Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus.
• Expertise in Synopsys IC compiler, Magma or Cadence SOC encounter physical design tools.
• Skill and experience in scripting using Tcl or Perl is highly desirable.
• Understand VLSI concepts perfectly.

Job Role: DFT and SOC Verification (Bangalore/Singapore)

Year of experience: Total 5+ years of hands-on project experience

Role and Responsibilities:

• Develop test-bench – compile scripts, automations for simulations
• Rollout pattern development flows/methodologies for various categories
• Contribute to test pattern generation methodology
• Write pattern specifications based on DFT requirements
• Pattern generation and pattern simulation & debug
• Generation of Functional patterns, characterization, IO, performance etc.
• Deliveries according to project schedules and with best quality
• Remotely support pattern debug support.
• Understand VLSI concepts perfectly.

Job Description:

• Experienced test pattern developer OR functional SoC verification engineer will be suitable for this job.
• Experienced in test-bench developments, module test-bench developments and exposure to various industry standard test-bench flows / methodologies
• Good experience in test pattern generation for functional, isolation, memory, power and timing characterization patterns
• Hands-on experience in SoC level test cases development, performance analysis and power analysis
• Good understanding of Microcontrollers & JTAG protocol
• Good understanding of functional simulation environments, simulator usage, debugging/trouble shooting skills
• Experience with gate-level-simulations and debug
• Experience in languages C , C++, and VHDL/Verilog
• Scripting experience – Make, PERL, TCL, etc

Job Role: IP & SOC Verification ( Bangalore/Singapore)

Year of experience: 4 to 8 yrs

Qualification: B.E or M.Tech in Electronics, Electrical, VLSI

HVLs/Tools: SV, UVM, C, Working Knowledge of ARM processors.

Domain: Networking, DDR2/3/4, Ethernet PCIe,

Job Description:

• Development of verification plans
• Verification environments
• Test cases and ensuring cov

Job Role: DFT

Experience: 4 to 10 yrs.

Qualification: B.E or M.Tech in Electronics, Electrical, VLSI

Job Description:

• Strong knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC –level for mixed signal designs.
• Experience in using Mentor DfT tools, Cadence RC and simulator tools
• Define DfT Strategy and Requirement Specification for the design
• DfT verification for gate-level and timing simulations
• Work cross sites with design team to define and implement DfT.
• Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.
• Work with STA engineer to define timing constraints for DfT modes
• Support Test engineer in silicon debug and pattern delivery for ATE
• Experience in RTL coding, shell scripting.
• Understand VLSI concepts perfectly.
• Experienced in handling analog DfT simulations
• Be fluent with all common concepts of DfT and DfT tools

Job Role: Synthesis/STA

Experience: 4+ years

Qualification: BTech/ MTech in ECE/ EEE from IITs/ RECs/ BITS

Job Description:

• Expertise in Sythesis using Synopsys DC/ Cadence RTL Compiler based tool set
• Expertise in Synthesis for High Performance , Low Power, Low Area based Flows
• Expertise in SDC Constraints Creation and constraints cleanup based on the timing issues
• Expertise in Formal & Low Power Verification using Synopsys/Cadence based tools.
• Expertise in Running PTSI/ETS tools for Timing Sign-off and generating timing ECO based on the timing issues
• Expertise in Multi-mode multi-corner STA analysis on SoC
• Skill and experience in scripting using Tcl or Perl is highly desirable

Job Role: Analog Mixed Signal Verification

Experience: 4 to 10 yrs.

Role:

• You will part of the circuit verification team to execute Analog circuit spice level verification, at block and full chip level.
• Need to be well verse with behavioral Verilog (Verilog AMS) model generation and their integration in full SoC.
• Will work closely with silicon design engineers and logic verification engineers for the circuit verification tasks and ensure deploys new product with the highest quality and shortest time to market.
• This work requires performing feasibility studies including idea creation, designing for verification, and developing new verification methodology

Job responsibilities:

• Write verification specifications, verification plans, and documentation
• Generate test bench and automate regression plans
• Be responsible for simulations, verifications, and debugging of circuit and logic designs (schematics, analog, RTL)
• Development of Behavioral models using Verilog and Verilog AMS (Analog Mixed Signal)
• Silicon evaluation and validation. Interface with cross-functional team and collaboration in all verification related activities

Job Role: RTL Design

Experience: 3 to 8 yrs.

Role:

Responsible for design and integration of ARM based processor SOC and subsystem

Job responsibilities:

• Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL.
• Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols
• Has good knowledge on various tools viz Spyglass, 0-in, DC-Compiler, Prime time, PTPX, Power-Artist,
• LEC etc Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus

Education: Required: Master’s, Vlsi & Embedded Systems or equivalent experience

More information about the openings:

Job code: GRSM25072016

Job Location: Bangalore / Singapore

Company Name: Will be disclosed to the interested candidates

Salary: Industry Standards

How to apply for this post?

For more information upload your resume here with proper job code and JOB ROLE, subject and details and tell us why you want to join. We will ask you to write code as part of your interview process, so be prepared! Our recruiters will be in touch.

Other openings can be checked in Job Vacancies

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